Method and apparatus for error detection and localization
A computer system reads data from selected locations in a memory while each address applied to the memory is temporarily stored in a register. If a data error is detected, two flipflops are set, one of which can generate and interrupt the central processing unit, and the other of which disables an A...
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creator | NICOL MARK D HELM GORDON L OLSON ANTHONY M |
description | A computer system reads data from selected locations in a memory while each address applied to the memory is temporarily stored in a register. If a data error is detected, two flipflops are set, one of which can generate and interrupt the central processing unit, and the other of which disables an AND gate through which a load signal is applied to the register in order to disable the register. An arrangement for resetting the second flipflop includes a third flipflop which is set and reset respectively at the beginning and end of each input/output cycle and which has an output coupled to one input of an AND gate having a further input to which is applied a signal selectively actuable by the central processing unit, the output of the AND gate and a system reset signal being applied to inputs of an OR gate which has its output connected to a reset input of the second flipflop. |
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If a data error is detected, two flipflops are set, one of which can generate and interrupt the central processing unit, and the other of which disables an AND gate through which a load signal is applied to the register in order to disable the register. An arrangement for resetting the second flipflop includes a third flipflop which is set and reset respectively at the beginning and end of each input/output cycle and which has an output coupled to one input of an AND gate having a further input to which is applied a signal selectively actuable by the central processing unit, the output of the AND gate and a system reset signal being applied to inputs of an OR gate which has its output connected to a reset input of the second flipflop.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1991</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19911210&DB=EPODOC&CC=US&NR=5072450A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19911210&DB=EPODOC&CC=US&NR=5072450A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NICOL; MARK D</creatorcontrib><creatorcontrib>HELM; GORDON L</creatorcontrib><creatorcontrib>OLSON; ANTHONY M</creatorcontrib><title>Method and apparatus for error detection and localization</title><description>A computer system reads data from selected locations in a memory while each address applied to the memory is temporarily stored in a register. If a data error is detected, two flipflops are set, one of which can generate and interrupt the central processing unit, and the other of which disables an AND gate through which a load signal is applied to the register in order to disable the register. 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If a data error is detected, two flipflops are set, one of which can generate and interrupt the central processing unit, and the other of which disables an AND gate through which a load signal is applied to the register in order to disable the register. An arrangement for resetting the second flipflop includes a third flipflop which is set and reset respectively at the beginning and end of each input/output cycle and which has an output coupled to one input of an AND gate having a further input to which is applied a signal selectively actuable by the central processing unit, the output of the AND gate and a system reset signal being applied to inputs of an OR gate which has its output connected to a reset input of the second flipflop.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | Method and apparatus for error detection and localization |
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