Debug Circuit Comparing Processor Instruction Set Operating Mode

A processor is operative to execute two or more instruction sets, each in a different instruction set operating mode. As each instruction is executed, debug circuit comparison the current instruction set operating mode to a target instruction set operating mode sent by a programmer, and outputs an a...

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Hauptverfasser: SARTORIUS THOMAS ANDREW, BURKE KEVIN CHARLES, RIZK NABIL AMIR, STREETT DAREN, DEBRUYNE LESLIE MARK, SMITH RODNEY WAYNE, STEMPEL BRIAN MICHAEL, SAPP KEVIN ALLEN
Format: Patent
Sprache:eng
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Zusammenfassung:A processor is operative to execute two or more instruction sets, each in a different instruction set operating mode. As each instruction is executed, debug circuit comparison the current instruction set operating mode to a target instruction set operating mode sent by a programmer, and outputs an alert or indication in they match. The alert or indication may additionally be dependent upon the instruction address following within a predetermined target address range. The alert or indication may comprise a breakpoint signal that halts execution and/or it is output as an external signal of the processor. The instruction address at which the processor detects a match in the instruction set operating modes may additionally be output. Additionally or alternatively, the alert or indication may comprise starting or stopping a trace operation, causing an exception, or any other known debugger function.