Formal Semantics and Proof Techniques for Optimizing VHDL Models

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to r...

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Bibliographische Detailangaben

Hauptverfasser:	Umamageswaran, Kothanda (VerfasserIn), Pandey, Sheetanshu L. (VerfasserIn), Wilsey, Philip A. (VerfasserIn)
Format:	Elektronisch E-Book
Sprache:	English
Veröffentlicht:	Boston, MA Springer US 1999
Schlagworte:	Engineering Circuits and Systems Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computer-aided engineering Electrical engineering Electronic circuits
Online-Zugang:	DE-634 URL des Erstveröffentlichers
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