Formal Semantics for VHDL

It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several...

Ausführliche Beschreibung

Bibliographische Detailangaben

Weitere Verfasser:	Kloos, Carlos Delgado (HerausgeberIn), Breuer, Peter T. (HerausgeberIn)
Format:	Elektronisch E-Book
Sprache:	English
Veröffentlicht:	Boston, MA Springer US 1995
Schriftenreihe:	The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 307
Schlagworte:	Engineering Circuits and Systems Programming Languages, Compilers, Interpreters Theory of Computation Computer Hardware Computing Methodologies Electrical Engineering Computer hardware Programming languages (Electronic computers) Computers Electrical engineering Electronic circuits VHDL
Online-Zugang:	DE-634 URL des Erstveröffentlichers
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