System-on-chip test architectures nanometer design for testability
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| Schriftenreihe: | The Morgan Kaufmann series in systems on silicon
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| 245 | 1 | 0 | |a System-on-chip test architectures |b nanometer design for testability |c ed. by Laung-Terng Wang ; Charles Stroud ; Nur A. Touba |
| 264 | 1 | |a Amsterdam [u.a.] |b Elsevier/Morgan Kaufmann Publ. |c 2008 | |
| 300 | |a XXXVI, 856 S. |b Ill., zahlr. graph. Darst. |c 24 cm | ||
| 336 | |b txt |2 rdacontent | ||
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| 490 | 0 | |a The Morgan Kaufmann series in systems on silicon | |
| 500 | |a Literaturangaben | ||
| 650 | 0 | |a Systems on a chip / Testing | |
| 650 | 0 | |a Integrated circuits / Very large scale integration / Testing | |
| 650 | 0 | |a Integrated circuits / Very large scale integration / Design | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Design | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Testing | |
| 650 | 4 | |a Systems on a chip |x Testing | |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
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| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Wang, Laung-Terng |e Sonstige |4 oth | |
| 700 | 1 | |a Stroud, Charles E. |e Sonstige |4 oth | |
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Datensatz im Suchindex
| _version_ | 1804137613926334464 |
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| adam_text | Contents
Preface xxi
In the Classroom xxvii
Acknowledgments xxix
Contributors xxxi
About the Editors xxxv
1 Introduction 1
Laung-Temg (L.-T.) Wang, Charles E. Stroud, and Nur A. Touba
1.1 Importance of System-on-Chip Testing 2
1.1.1 Yield and Reject Rate 5
1.1.2 Reliability and System Availability 6
1.2 Basics of SOC Testing 8
1.2.1 Boundary Scan (IEEE 1149.1 Standard) 9
1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard) 11
1.2.3 Boundary-Scan Accessible Embedded Instruments
(IEEEP1687) 13
1.2.4 Core-Based Testing (IEEE 1500 Standard) 13
1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard) 17
1.3 Basics of Memory Testing 20
1.4 SOC Design Examples 24
1.4.1 BioMEMS Sensor 25
1.4.2 Network-on-Chip Processor 27
1.5 About This Book 30
1.5.1 DFT Architectures 30
1.5.2 New Fault Models and Advanced Techniques 31
1.5.3 Yield and Reliability Enhancement 32
1.5.4 Nanotechnology Testing Aspects 33
1.6 Exercises 33
Acknowledgments 36
References 36
vi Contents
2 Digital Test Architectures 41
Laung-Terng (L.-T.) Wang
2.1 Introduction 41
2.2 Scan Design 43
2.2.1 Scan Architectures 44
2.2.1.1 Muxed-D Scan Design 44
2.2.1.2 Clocked-Scan Design 46
2.2.1.3 LSSD Scan Design 47
2.2.1.4 Enhanced-Scan Design 48
2.2.2 Low-Power Scan Architectures 50
2.2.2.1 Reduced-Voltage Low-Power Scan Design .... 50
2.2.2.2 Reduced-Frequency Low-Power
Scan Design 50
2.2.2.3 Multi-Phase or Multi-Duty Low-Power
Scan Design 50
2.2.2.4 Bandwidth-Matching Low-Power
Scan Design 51
2.2.2.5 Hybrid Low-Power Scan Design 52
2.2.3 At-Speed Scan Architectures 52
2.3 Logic Built-in Self-Test 57
2.3.1 Logic BIST Architectures 58
2.3.1.1 Self-Testing Using MISR and Parallel SRSG
(STUMPS) 58
2.3.1.2 Concurrent Built-in Logic Block Observer
(CBILBO) 59
2.3.2 Coverage-Driven Logic BIST Architectures 61
2.3.2.1 Weighted Pattern Generation 61
2.3.2.2 Test Point Insertion 62
2.3.2.3 Mixed-Mode BIST 64
2.3.2.4 Hybrid BIST 65
2.3.3 Low-Power Logic BIST Architectures 66
2.3.3.1 Low-Transition BIST Design 66
2.3.3.2 Test-Vector-Inhibiting BIST Design 67
2.3.3.3 Modified LFSR Low-Power BIST Design 67
2.3.4 At-Speed Logic BIST Architectures 68
2.3.4.1 Single-Capture 68
2.3.4.2 Skewed-Load 70
2.3.4.3 Double-Capture 73
2.3.5 Industry Practices 75
2.4 Test Compression 76
2.4.1 Circuits for Test Stimulus Compression 77
2.4.1.1 Linear-Decompression-Based Schemes 77
2.4.1.2 Broadcast-Scan-Based Schemes 81
2.4.1.3 Comparison 85
Contents vii
2.4.2 Circuits for Test Response Compaction 87
2.4.2.1 Space Compaction 88
2.4.2.2 Time Compaction 92
2.4.2.3 Mixed Time and Space Compaction 93
2.4.3 Low-Power Test Compression Architectures 94
2.4.4 Industry Practices 95
2.5 Random-Access Scan Design 97
2.5.1 Random-Access Scan Architectures 98
2.5.1.1 Progressive Random-Access
Scan Design 100
2.5.1.2 Shift-Addressable Random-Access
Scan Design 101
2.5.2 Test Compression RAS Architectures 103
2.5.3 At-Speed RAS Architectures 105
2.6 Concluding Remarks 106
2.7 Exercises 106
Acknowledgments 110
References Ill
3 Fault-Tolerant Design 123
Nur A. Touba
3.1 Introduction 123
3.2 Fundamentals of Fault Tolerance 124
3.2.1 Reliability 125
3.2.2 Mean Time to Failure (MTTF) 126
3.2.3 Maintainability 127
3.2.4 Availability 127
3.3 Fundamentals of Coding Theory 129
3.3.1 Linear Block Codes 129
3.3.2 Unidirectional Codes 135
3.3.2.1 Two-Rail Codes 135
3.3.2.2 Berger Codes 136
3.3.2.3 Constant Weight Codes 136
3.3.3 Cyclic Codes 137
3.4 Fault Tolerance Schemes 142
3.4.1 Hardware Redundancy 142
3.4.1.1 Static Redundancy 142
3.4.1.2 Dynamic Redundancy 146
3.4.1.3 Hybrid Redundancy 148
3.4.2 Time Redundancy 150
3.4.2.1 Repeated Execution 150
3.4.2.2 Multiple Sampling of Outputs 151
3.4.2.3 Diverse Recomputation 152
viii Contents
3.4.3 Information Redundancy 153
3.4.3.1 Error Detection 153
3.4.3.2 Error Correction 160
3.5 Industry Practices 163
3.6 Concluding Remarks 165
3.7 Exercises 165
Acknowledgments 168
References 168
4 System/Network-on-Chip Test Architectures 171
Chunsheng Liu, Krishnendu Chakrabarty, and Wen-Ben Jone
4.1 Introduction 172
4.2 System-on-Chip (SOC) Testing 175
4.2.1 Modular Testing of SOCs 175
4.2.2 Wrapper Design and Optimization 177
4.2.3 TAM Design and Optimization 179
4.2.4 Test Scheduling 181
4.2.5 Modular Testing of Mixed-Signal SOCs 185
4.2.6 Modular Testing of Hierarchical SOCs 188
4.2.7 Wafer-Sort Optimization for Core-Based SOCs 191
4.3 Network-on-Chip (NOC) Testing 192
4.3.1 NOC Architectures 192
4.3.2 Testing of Embedded Cores 194
4.3.2.1 Reuse of On-Chip Network for Testing 194
4.3.2.2 Test Scheduling 196
4.3.2.3 Test Access Methods and Test Interface 197
4.3.2.4 Efficient Reuse of Network 198
4.3.2.5 Power-Aware and Thermal-Aware Testing .... 202
4.3.3 Testing of On-Chip Networks 203
4.3.3.1 Testing of Interconnect Infrastructures 203
4.3.3.2 Testing of Routers 205
4.3.3.3 Testing of Network Interfaces and
Integrated System Testing 208
4.4 Design and Test Practice: Case Studies 209
4.4.1 SOC Testing for PNX8550 System Chip 210
4.4.2 NOC Testing for a High-End TV System 212
4.5 Concluding Remarks 215
4.6 Exercises 216
Acknowledgments 217
References 217
Contents ix
5 SIP Test Architectures 225
Philippe Cauvet, Michel Renovell, and Serge Bernard
5.1 Introduction 226
5.1.1 SIP Definition 226
5.1.2 SIP Examples 227
5.1.3 Yield and Quality Challenges 230
5.1.4 Test Strategy 233
5.2 Bare Die Test 235
5.2.1 Mechanical Probing Techniques 235
5.2.2 Electrical Probing Techniques 237
5.2.3 Reliability Screens 240
5.3 Functional System Test 242
5.3.1 Path-Based Testing 242
5.3.2 Loopback Techniques: DFT and DSP 245
5.4 Test of Embedded Components 246
5.4.1 SIP Test Access Port 247
5.4.2 Interconnections 250
5.4.3 Digital and Memory Dies 251
5.4.4 Analog and RF Components 253
5.4.4.1 Test Equipment Issues 253
5.4.4.2 Test of Analog, Mixed-Signal,
and RF Dies 254
5.4.5 MEMS 255
5.5 Concluding Remarks 257
5.6 Exercises 257
Acknowledgments 258
References 258
6 Delay Testing 263
Duncan M. (Hank) Walker and Michael S. Hsiao
6.1 Introduction 263
6.2 Delay Test Application 265
6.2.1 Enhanced Scan 266
6.2.2 Muxed-D Scan 266
6.2.3 Scan Clocking 266
6.2.4 Faster-Than-At-Speed Testing 268
6.3 Delay Fault Models 269
6.3.1 Transition Fault Model 269
6.3.2 Inline-Delay Fault Model 270
6.3.3 Gate-Delay Fault Model 270
6.3.4 Path-Delay Fault Model 270
6.3.5 Defect-Based Delay Fault Models 271
X Contents
6.4 Delay Test Sensitization 276
6.5 Delay Fault Simulation 277
6.5.1 Transition Fault Simulation 277
6.5.2 Gate/Line Delay Fault Simulation 277
6.5.3 Path-Delay Fault Simulation 278
6.5.4 Defect-Based Delay Fault Model Simulation 278
6.6 Delay Fault Test Generation 280
6.6.1 Transition/Inline Fault ATPG 280
6.6.2 Gate-Delay Fault ATPG 282
6.6.3 Path-Delay Fault ATPG 282
6.6.4 K Longest Paths per Gate (KLPG) ATPG 283
6.7 Pseudo-Functional Testing to Avoid Over-Testing 288
6.7.1 Computing Constraints 290
6.7.1.1 Pair-Wise Constraints 291
6.7.1.2 Multiliteral Constraints 291
6.7.2 Constrained ATPG 293
6.8 Concluding Remarks 294
6.9 Exercises 295
Acknowledgments 299
References 300
7 Low-Power Testing 307
Patrick Girard, Xiaoqing Wen, and Nur A. Touba
7.1 Introduction 307
7.2 Energy and Power Modeling 309
7.2.1 Basics of Circuit Theory 310
7.2.2 Terminology 311
7.2.3 Test-Power Modeling and Evaluation 312
7.3 Test Power Issues 313
7.3.1 Thermal Effects 314
7.3.2 Noise Phenomena 314
7.3.3 Miscellaneous Issues 315
7.4 Low-Power Scan Testing 316
7.4.1 Basics of Scan Testing 316
7.4.2 ATPG and X-Filling Techniques 318
7.4.3 Low-Power Test Vector Compaction 320
7.4.4 Shift Control Techniques 321
7.4.5 Scan Cell Ordering 322
7.4.6 Scan Architecture Modification 324
7.4.7 Scan Clock Splitting 326
7.5 Low-Power Built-in Self-Test 328
7.5.1 Basics of Logic BIST 328
7.5.2 LFSR Tuning 329
7.5.3 Low-Power Test Pattern Generators 330
Contents xi
7.5.4 Vector Filtering BIST 331
7.5.5 Circuit Partitioning 332
7.5.6 Power-Aware Test Scheduling 334
7.6 Low-Power Test Data Compression 335
7.6.1 Coding-Based Schemes 336
7.6.2 Linear-Decompression-Based
Schemes 336
7.6.3 Broadcast-Scan-Based Schemes 337
7.7 Low-Power RAM Testing 339
7.8 Concluding Remarks 341
7.9 Exercises 342
Acknowledgments 344
References 344
8 Coping with Physical Failures, Soft Errors,
and Reliability Issues 351
Laung-Terng (L.-T.) Wang, Mehrdad Nourani, and T. M. Mak
8.1 Introduction 352
8.2 Signal Integrity 354
8.2.1 Basic Concept of Integrity Loss 354
8.2.2 Sources of Integrity Loss 356
8.2.2.1 Interconnects 356
8.2.2.2 Power Supply Noise 358
8.2.2.3 Process Variations 358
8.2.3 Integrity Loss Sensors/Monitors 360
8.2.3.1 Current Sensor 360
8.2.3.2 Power Supply Noise Monitor 361
8.2.3.3 Noise Detector (ND) Sensor 362
8.2.3.4 Integrity Loss Sensor (ILS) 362
8.2.3.5 Jitter Monitor 363
8.2.3.6 Process Variation Sensor 364
8.2.4 Readout Architectures 365
8.2.4.1 BIST-Based Architecture 365
8.2.4.2 Scan-Based Architecture 367
8.2.4.3 PV-Test Architecture 368
8.3 Manufacturing Defects, Process Variations, and.Reliability 370
8.3.1 Fault Detection 370
8.3.1.1 Structural Tests 371
8.3.1.2 Defect-Based Tests 372
8.3.1.3 Functional Tests 378
8.3.2 Reliability Stress 379
8.3.3 Redundancy and Memory Repair 381
8.3.4 Process Sensors and Adaptive Design 382
8.3.4.1 Process Variation Sensor 383
xii Contents
8.3.4.2 Thermal Sensor 383
8.3.4.3 Dynamic Voltage Scaling 385
8.4 Soft Errors 386
8.4.1 Sources of Soft Errors and SER Trends 387
8.4.2 Coping with Soft Errors 390
8.4.2.1 Fault Tolerance 390
8.4.2.2 Error-Resilient Microarchitectures 394
8.4.2.3 Soft Error Mitigation 398
8.5 Defect and Error Tolerance 402
8.5.1 Defect Tolerance 404
8.5.2 Error Tolerance 405
8.6 Concluding Remarks 407
8.7 Exercises 407
Acknowledgments 409
References 409
9 Design for Manufacturability and Yield 423
Robert C. Aitken
9.1 Introduction 423
9.2 Yield 426
9.3 Components of Yield 427
9.3.1 Yield Models 428
9.3.2 Yield and Repair 429
9.4 Photolithography 430
9.5 DFMandDFY 433
9.5.1 Photolithography 435
9.5.2 Critical Area 439
9.5.3 Yield Variation over Time 441
9.5.4 DFT and DFM/DFY 444
9.6 Variability 445
9.6.1 Sources of Variability 445
9.6.2 Deterministic versus Random Variability 446
9.6.3 Variability versus Defectivity 448
9.6.4 Putting It All Together 449
9.7 Metrics for DFX 449
9.7.1 The Ideal Case 450
9.7.2 Potential DFY Metrics 452
9.7.2.1 Critical Area 452
9.7.2.2 RET-Based Metrics 452
9.7.2.3 Example DRC-Based Metrics for DFM 454
9.8 Concluding Remarks 456
9.9 Exercises 457
Acknowledgments 458
References 459
Contents xiii
10 Design for Debug and Diagnosis 463
T. M. Mak and Srikanth Venkataraman
10.1 Introduction 463
10.1.1 What Are Debug and Diagnosis? 464
10.1.2 Where Is Diagnosis Used? 465
10.1.3 IC-Level Debug and Diagnosis 465
10.1.4 Silicon Debug versus Defect Diagnosis 466
10.1.5 Design for Debug and Diagnosis 467
10.2 Logic Design for Debug and Diagnosis
(DFD) Structures 468
10.2.1 Scan 468
10.2.2 Observation-Only Scan 469
10.2.3 Observation Points with Multiplexers 471
10.2.4 Array Dump and Trace Logic Analyzer 472
10.2.5 Clock Control 473
10.2.6 Partitioning, Isolation, and De-featuring 475
10.2.7 Reconfigurable Logic 476
10.3 Probing Technologies 476
10.3.1 Mechanical Probing 477
10.3.2 Injection-Based Probing 478
10.3.2.1 E-beam Probing 478
10.3.2.2 Laser Voltage Probing 479
10.3.3 Emission-Based Probing 483
10.3.3.1 Infrared Emission
Microscopy (IREM) 483
10.3.3.2 Picosecond Imaging Circuit
Analysis (PICA) 485
10.3.3.3 Time Resolved Emissions (TRE) 486
10.4 Circuit Editing 487
10.4.1 Focused Ion Beam 487
10.4.2 Layout-Database-Driven Navigation System 488
10.4.3 Spare Gates and Spare Wires 489
10.5 Physical DFD Structures 490
10.5.1 Physical DFD for Pico-Probing 490
10.5.2 Physical DFD for E-Beam 491
10.5.3 Physical DFD for FIB and Probing 492
10.6 Diagnosis and Debug Process 492
10.6.1 Diagnosis Techniques and Strategies 495
10.6.2 Silicon Debug Process and Flow 496
10.6.3 Debug Techniques and Methodology 497
10.7 Concluding Remarks 498
10.8 Exercises 499
Acknowledgments 500
References 500
xiv Contents
11 Software-Based Self-Testing 505
Jiun-Lang Huang and Kwang-Ting (Tim) Cheng
11.1 Introduction 506
11.2 Software-Based Self-Testing Paradigm 507
11.2.1 Self-Test Flow 508
11.2.2 Comparison with Structural BIST 509
11.3 Processor Functional Fault Self-Testing 510
11.3.1 Processor Model 510
11.3.2 Functional-Level Fault Models 512
11.3.3 Test Generation Procedures 513
11.3.3.1 Test Generation for Register
Decoding Fault 513
11.3.3.2 Test Generation for Instruction
Decoding and Control Fault 514
11.3.3.3 Test Generation for Data Transfer
and Storage Function 515
11.3.3.4 Test Generation for Data Manipulation
Function 516
11.3.3.5 Test Generation Complexity 516
11.4 Processor Structural Fault Self-Testing 516
11.4.1 Test Flow 516
11.4.1.1 Test Preparation 516
11.4.1.2 Self-Testing 517
11.4.2 Stuck-At Fault Testing 518
11.4.2.1 Instruction-Imposed I/O Constraint
Extraction 518
11.4.2.2 Constrained Component
Test Generation 519
11.4.2.3 Test Program Synthesis 521
11.4.2.4 Processor Self-Testing 522
11.4.3 Test Program Synthesis Using Virtual Constraint
Circuits (VCCs) 523
11.4.4 Delay Fault Testing 526
11.4.4.1 Functionally Untestable Delay Faults .... 526
11.4.4.2 Constraint Extraction 527
11.4.4.3 Test Program Generation 528
11.4.5 Functional Random Instruction Testing 529
11.5 Processor Self-Diagnosis 530
11.5.1 Challenges to SBST-Based Processor Diagnosis 530
11.5.2 Diagnostic Test Program Generation 531
11.6 Testing Global Interconnect 533
11.6.1 Maximum Aggressor (MA) Fault Model 533
11.6.2 Processor-Based Address and Data Bus Testing 534
Contents xv
11.6.2.1 Data Bus Testing 534
11.6.2.2 Address Bus Testing 535
11.6.3 Processor-Based Functional MA Testing 536
11.7 Testing Nonprogrammable Cores 536
11.7.1 Preprocessing Phase 538
11.7.2 Core Test Phase 538
11.8 Instruction-Level DFT 538
11.8.1 Instruction-Level DFT Concept 538
11.8.2 Testability Instructions 539
11.8.3 Test Optimization Instructions 541
11.9 DSP-Based Analog/Mixed-Signal Component Testing 541
11.10 Concluding Remarks 543
11.11 Exercises 544
Acknowledgments 545
References 545
12 Field Programmable Gate Array Testing 549
Charles E. Stroud
12.1 Overview of FPGAs 549
12.1.1 Architecture 550
12.1.2 Configuration 554
12.1.3 The Testing Problem 556
12.2 Testing Approaches 558
12.2.1 External Testing and Built-in Self-Test 559
12.2.2 Online and Offline Testing 560
12.2.3 Application Dependent and Independent Testing .... 561
12.3 BIST of Programmable Resources 562
12.3.1 Logic Resources 563
12.3.1.1 Programmable Logic Blocks 567
12.3.1.2 Input/Output Cells 570
12.3.1.3 Specialized Cores 571
12.3.1.4 Diagnosis 575
12.3.2 Interconnect Resources 578
12.4 Embedded Processor-Based Testing 583
12.5 Concluding Remarks 585
12.6 Exercises 586
Acknowledgments 587
References 587
13 MEMS Testing 59^1
Ramesh Ramadoss, Robert Dean, and Xingguo Xiong
13.1 Introduction 592
13.2 MEMS Testing Considerations 593
xvi Contents
13.3 Test Methods and Instrumentation for MEMS 594
13.3.1 Electrical Test 595
13.3.2 Optical Test Methods 596
13.3.3 Material Property Measurements 598
13.3.4 Failure Modes and Analysis 599
13.3.5 Mechanical Test Methods 600
13.3.6 Environmental Testing 607
13.4 RF MEMS Devices 609
13.4.1 RF MEMS Switches 610
13.4.2 RF MEMS Resonators 611
13.5 Optical MEMS Devices 614
13.6 Fluidic MEMS Devices 616
13.6.1 MEMS Pressure Sensor 617
13.6.2 MEMS Humidity Sensor 618
13.7 Dynamic MEMS Devices 620
13.7.1 MEMS Microphone 620
13.7.2 MEMS Accelerometer 621
13.7.3 MEMS Gyroscope 622
13.8 Testing Digital Microfluidic Biochips 625
13.8.1 Overview of Digital Microfluidic Biochips 626
13.8.2 Fault Modeling 627
13.8.3 Test Techniques 628
13.8.4 Application to a Fabricated Biochip 631
13.9 DFT and BIST for MEMS 633
13.9.1 Overview of DFT and BIST Techniques 633
13.9.2 MEMS BIST Examples 637
13.10 Concluding Remarks 643
13.11 Exercises 644
Acknowledgments 646
References 646
14 High-Speed I/O Interfaces 653
Mike Peng Li, T. M. Mak, and Kwang-Ting (Tim) Cheng
14.1 Introduction 654
14.2 High-Speed I/O Architectures 657
14.2.1 Global Clock I/O Architectures 657
14.2.2 Source Synchronous I/O Architectures 658
14.2.3 Embedded Clock I/O Architectures 660
14.2.3.1 Jitter Components 661
14.2.3.2 Jitter Separation 662
14.2.3.3 Jitter, Noise, and Bit-Error-Rate
Interactions 666
14.3 Testing of I/O Interfaces 668
14.3.1 Testing of Global Clock I/O 669
Contents xvii
14.3.2 Testing of Source Synchronous I/O 669
14.3.3 Testing of Embedded Clock High-Speed Serial I/O ... 671
14.3.3.1 Transmitter 671
14.3.3.2 Channel or Medium 673
14.3.3.3 Receiver 675
14.3.3.4 Reference Clock 677
14.3.3.5 System-Level Bit-Error-Rate
Estimation 678
14.3.3.6 Tester Apparatus Considerations 678
14.4 DFT-Assisted Testing 680
14.4.1 AC Loopback Testing 681
14.4.2 High-Speed Serial-Link Loopback Testing 683
14.4.3 Testing the Equalizers 686
14.5 System-Level Interconnect Testing 690
14.5.1 Interconnect Testing with Boundary Scan 690
14.5.2 Interconnect Testing with High-Speed
Boundary Scan 691
14.5.3 Interconnect Built-in Self-Test 693
14.6 Future Challenges 694
14.7 Concluding Remarks 695
14.8 Exercises 696
Acknowledgments 697
References 697
15 Analog and Mixed-Signal Test Architectures 703
F. Foster Dai and Charles E. Stroud
15.1 Introduction 704
15.2 Analog Functional Testing 705
15.2.1 Frequency Response Testing 705
15.2.2 Linearity Testing 707
15.2.3 Signal-to-Noise Ratio Testing 709
15.2.4 Quantization Noise 710
15.2.5 Phase Noise 712
15.2.6 Noise in Phase-Locked Loops 715
15.2.6.1 In-Band PLL Phase Noise 716
15.2.6.2 Out-Band PLL Phase Noise 718
15.2.6.3 Optimal Loop Setting 718
15.2.7 DAC Nonlinearity Testing 719
15.3 Analog and Mixed-Signal Test Architectures 720
15.4 Defect-Oriented Mixed-Signal BIST Approaches 724
15.5 FFT-Based Mixed-Signal BIST 727
15.5.1 FFT 727
15.5.2 Inverse FFT 729
15.5.3 FFT-Based BIST Architecture 729
xviii Contents
15.5.4 FFT-Based Output Response Analysis 730
15.5.5 FFT-Based Test Pattern Generation 731
15.6 Direct Digital Synthesis BIST 733
15.6.1 DDS-Based BIST Architecture 734
15.6.2 Frequency Response Test and Measurement 736
15.6.3 Linearity Test and Measurement 738
15.6.4 SNR and Noise Figure Measurement 739
15.7 Concluding Remarks 739
15.8 Exercises 740
Acknowledgments 741
References 741
16 RF Testing 745
Soumendu Bhattacharya and Abhijit Chatterjee
16.1 Introduction 746
16.1.1 RF Basics 746
16.1.2 RF Applications 748
16.2 Key Specifications for RF Systems 750
16.2.1 Test Instrumentation 750
16.2.1.1 Spectrum Analyzer 751
16.2.1.2 Network Analyzer 752
16.2.1.3 Noise Figure Meter 753
16.2.1.4 Phase Meter 755
16.2.2 Test Flow in Industry 755
16.2.2.1 Design and Fabrication 756
16.2.2.2 Characterization Test 756
16.2.2.3 Production Test 756
16.2.3 Characterization Test and Production Test 757
16.2.3.1 Accuracy 757
16.2.3.2 Time Required for Testing 758
16.2.3.3 Cost of Testing 758
16.2.4 Circuit-Level Specifications 758
16.2.4.1 Gain 759
16.2.4.2 Harmonics and Third-Order
Intercept Point (IP3) 759
16.2.4.3 1-dB Compression Point (P_ldB) 763
16.2.4.4 Total Harmonic Distortion (THD) 763
16.2.4.5 Gain Flatness 764
16.2.4.6 Noise Figure 765
16.2.4.7 Sensitivity and Dynamic Range 767
16.2.4.8 Local Oscillator Leakage 768
16.2.4.9 Phase Noise 768
16.2.4.10 Adjacent Channel Power Ratio 769
Contents xix
16.2.5 System-Level Specifications 770
16.2.5.1 I-Q Mismatch 770
16.2.5.2 Error Vector Magnitude 771
16.2.5.3 Modulation Error Ratio 772
16.2.5.4 Bit Error Rate 773
16.2.6 Structure of RF Systems 774
16.3 Test Hardware: Tester and DIB/PIB 776
16.4 Repeatability and Accuracy 779
16.5 Industry Practices for High-Volume Manufacturing 782
16.5.1 Test Cost Analysis 783
16.5.2 Key Trends 784
16.6 Concluding Remarks 785
16.7 Exercises 786
Acknowledgments 787
References 788
17 Testing Aspects of Nanotechnology Trends 791
Mehdi B. Tahoori, Niraj K. Jha, and R. Iris Bahar
17.1 Introduction 792
17.2 Resonant Tunneling Diodes and Quantum-Dot
Cellular Automata 794
17.2.1 Testing Threshold Networks with Application
toRTDs 795
17.2.2 Testing Majority Networks with Application
toQCA 799
17.3 Crossbar Array Architectures 807
17.3.1 Hybrid Nanoscale/CMOS Structures 810
17.3.1.1 ThenanoPLA 810
17.3.1.2 Molecular CMOS (CMOL) 813
17.3.2 Built-in Self-Test 815
17.3.3 Simultaneous Configuration and Test 817
17.4 Carbon Nanotube (CNT) Field Effect Transistors 820
17.4.1 Imperfection-Immune Circuits for
Misaligned CNTs 820
17.4.2 Robust Circuits for Metallic CNTs 824
17.5 Concluding Remarks 826
Acknowledgments 826
References 827
Index 833
|
| adam_txt |
Contents
Preface xxi
In the Classroom xxvii
Acknowledgments xxix
Contributors xxxi
About the Editors xxxv
1 Introduction 1
Laung-Temg (L.-T.) Wang, Charles E. Stroud, and Nur A. Touba
1.1 Importance of System-on-Chip Testing 2
1.1.1 Yield and Reject Rate 5
1.1.2 Reliability and System Availability 6
1.2 Basics of SOC Testing 8
1.2.1 Boundary Scan (IEEE 1149.1 Standard) 9
1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard) 11
1.2.3 Boundary-Scan Accessible Embedded Instruments
(IEEEP1687) 13
1.2.4 Core-Based Testing (IEEE 1500 Standard) 13
1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard) 17
1.3 Basics of Memory Testing 20
1.4 SOC Design Examples 24
1.4.1 BioMEMS Sensor 25
1.4.2 Network-on-Chip Processor 27
1.5 About This Book 30
1.5.1 DFT Architectures 30
1.5.2 New Fault Models and Advanced Techniques 31
1.5.3 Yield and Reliability Enhancement 32
1.5.4 Nanotechnology Testing Aspects 33
1.6 Exercises 33
Acknowledgments 36
References 36
vi Contents
2 Digital Test Architectures 41
Laung-Terng (L.-T.) Wang
2.1 Introduction 41
2.2 Scan Design 43
2.2.1 Scan Architectures 44
2.2.1.1 Muxed-D Scan Design 44
2.2.1.2 Clocked-Scan Design 46
2.2.1.3 LSSD Scan Design 47
2.2.1.4 Enhanced-Scan Design 48
2.2.2 Low-Power Scan Architectures 50
2.2.2.1 Reduced-Voltage Low-Power Scan Design . 50
2.2.2.2 Reduced-Frequency Low-Power
Scan Design 50
2.2.2.3 Multi-Phase or Multi-Duty Low-Power
Scan Design 50
2.2.2.4 Bandwidth-Matching Low-Power
Scan Design 51
2.2.2.5 Hybrid Low-Power Scan Design 52
2.2.3 At-Speed Scan Architectures 52
2.3 Logic Built-in Self-Test 57
2.3.1 Logic BIST Architectures 58
2.3.1.1 Self-Testing Using MISR and Parallel SRSG
(STUMPS) 58
2.3.1.2 Concurrent Built-in Logic Block Observer
(CBILBO) 59
2.3.2 Coverage-Driven Logic BIST Architectures 61
2.3.2.1 Weighted Pattern Generation 61
2.3.2.2 Test Point Insertion 62
2.3.2.3 Mixed-Mode BIST 64
2.3.2.4 Hybrid BIST 65
2.3.3 Low-Power Logic BIST Architectures 66
2.3.3.1 Low-Transition BIST Design 66
2.3.3.2 Test-Vector-Inhibiting BIST Design 67
2.3.3.3 Modified LFSR Low-Power BIST Design 67
2.3.4 At-Speed Logic BIST Architectures 68
2.3.4.1 Single-Capture 68
2.3.4.2 Skewed-Load 70
2.3.4.3 Double-Capture 73
2.3.5 Industry Practices 75
2.4 Test Compression 76
2.4.1 Circuits for Test Stimulus Compression 77
2.4.1.1 Linear-Decompression-Based Schemes 77
2.4.1.2 Broadcast-Scan-Based Schemes 81
2.4.1.3 Comparison 85
Contents vii
2.4.2 Circuits for Test Response Compaction 87
2.4.2.1 Space Compaction 88
2.4.2.2 Time Compaction 92
2.4.2.3 Mixed Time and Space Compaction 93
2.4.3 Low-Power Test Compression Architectures 94
2.4.4 Industry Practices 95
2.5 Random-Access Scan Design 97
2.5.1 Random-Access Scan Architectures 98
2.5.1.1 Progressive Random-Access
Scan Design 100
2.5.1.2 Shift-Addressable Random-Access
Scan Design 101
2.5.2 Test Compression RAS Architectures 103
2.5.3 At-Speed RAS Architectures 105
2.6 Concluding Remarks 106
2.7 Exercises 106
Acknowledgments 110
References Ill
3 Fault-Tolerant Design 123
Nur A. Touba
3.1 Introduction 123
3.2 Fundamentals of Fault Tolerance 124
3.2.1 Reliability 125
3.2.2 Mean Time to Failure (MTTF) 126
3.2.3 Maintainability 127
3.2.4 Availability 127
3.3 Fundamentals of Coding Theory 129
3.3.1 Linear Block Codes 129
3.3.2 Unidirectional Codes 135
3.3.2.1 Two-Rail Codes 135
3.3.2.2 Berger Codes 136
3.3.2.3 Constant Weight Codes 136
3.3.3 Cyclic Codes 137
3.4 Fault Tolerance Schemes 142
3.4.1 Hardware Redundancy 142
3.4.1.1 Static Redundancy 142
3.4.1.2 Dynamic Redundancy 146
3.4.1.3 Hybrid Redundancy 148
3.4.2 Time Redundancy 150
3.4.2.1 Repeated Execution 150
3.4.2.2 Multiple Sampling of Outputs 151
3.4.2.3 Diverse Recomputation 152
viii Contents
3.4.3 Information Redundancy 153
3.4.3.1 Error Detection 153
3.4.3.2 Error Correction 160
3.5 Industry Practices 163
3.6 Concluding Remarks 165
3.7 Exercises 165
Acknowledgments 168
References 168
4 System/Network-on-Chip Test Architectures 171
Chunsheng Liu, Krishnendu Chakrabarty, and Wen-Ben Jone
4.1 Introduction 172
4.2 System-on-Chip (SOC) Testing 175
4.2.1 Modular Testing of SOCs 175
4.2.2 Wrapper Design and Optimization 177
4.2.3 TAM Design and Optimization 179
4.2.4 Test Scheduling 181
4.2.5 Modular Testing of Mixed-Signal SOCs 185
4.2.6 Modular Testing of Hierarchical SOCs 188
4.2.7 Wafer-Sort Optimization for Core-Based SOCs 191
4.3 Network-on-Chip (NOC) Testing 192
4.3.1 NOC Architectures 192
4.3.2 Testing of Embedded Cores 194
4.3.2.1 Reuse of On-Chip Network for Testing 194
4.3.2.2 Test Scheduling 196
4.3.2.3 Test Access Methods and Test Interface 197
4.3.2.4 Efficient Reuse of Network 198
4.3.2.5 Power-Aware and Thermal-Aware Testing . 202
4.3.3 Testing of On-Chip Networks 203
4.3.3.1 Testing of Interconnect Infrastructures 203
4.3.3.2 Testing of Routers 205
4.3.3.3 Testing of Network Interfaces and
Integrated System Testing 208
4.4 Design and Test Practice: Case Studies 209
4.4.1 SOC Testing for PNX8550 System Chip 210
4.4.2 NOC Testing for a High-End TV System 212
4.5 Concluding Remarks 215
4.6 Exercises 216
Acknowledgments 217
References 217
Contents ix
5 SIP Test Architectures 225
Philippe Cauvet, Michel Renovell, and Serge Bernard
5.1 Introduction 226
5.1.1 SIP Definition 226
5.1.2 SIP Examples 227
5.1.3 Yield and Quality Challenges 230
5.1.4 Test Strategy 233
5.2 Bare Die Test 235
5.2.1 Mechanical Probing Techniques 235
5.2.2 Electrical Probing Techniques 237
5.2.3 Reliability Screens 240
5.3 Functional System Test 242
5.3.1 Path-Based Testing 242
5.3.2 Loopback Techniques: DFT and DSP 245
5.4 Test of Embedded Components 246
5.4.1 SIP Test Access Port 247
5.4.2 Interconnections 250
5.4.3 Digital and Memory Dies 251
5.4.4 Analog and RF Components 253
5.4.4.1 Test Equipment Issues 253
5.4.4.2 Test of Analog, Mixed-Signal,
and RF Dies 254
5.4.5 MEMS 255
5.5 Concluding Remarks 257
5.6 Exercises 257
Acknowledgments 258
References 258
6 Delay Testing 263
Duncan M. (Hank) Walker and Michael S. Hsiao
6.1 Introduction 263
6.2 Delay Test Application 265
6.2.1 Enhanced Scan 266
6.2.2 Muxed-D Scan 266
6.2.3 Scan Clocking 266
6.2.4 Faster-Than-At-Speed Testing 268
6.3 Delay Fault Models 269
6.3.1 Transition Fault Model 269
6.3.2 Inline-Delay Fault Model 270
6.3.3 Gate-Delay Fault Model 270
6.3.4 Path-Delay Fault Model 270
6.3.5 Defect-Based Delay Fault Models 271
X Contents
6.4 Delay Test Sensitization 276
6.5 Delay Fault Simulation 277
6.5.1 Transition Fault Simulation 277
6.5.2 Gate/Line Delay Fault Simulation 277
6.5.3 Path-Delay Fault Simulation 278
6.5.4 Defect-Based Delay Fault Model Simulation 278
6.6 Delay Fault Test Generation 280
6.6.1 Transition/Inline Fault ATPG 280
6.6.2 Gate-Delay Fault ATPG 282
6.6.3 Path-Delay Fault ATPG 282
6.6.4 K Longest Paths per Gate (KLPG) ATPG 283
6.7 Pseudo-Functional Testing to Avoid Over-Testing 288
6.7.1 Computing Constraints 290
6.7.1.1 Pair-Wise Constraints 291
6.7.1.2 Multiliteral Constraints 291
6.7.2 Constrained ATPG 293
6.8 Concluding Remarks 294
6.9 Exercises 295
Acknowledgments 299
References 300
7 Low-Power Testing 307
Patrick Girard, Xiaoqing Wen, and Nur A. Touba
7.1 Introduction 307
7.2 Energy and Power Modeling 309
7.2.1 Basics of Circuit Theory 310
7.2.2 Terminology 311
7.2.3 Test-Power Modeling and Evaluation 312
7.3 Test Power Issues 313
7.3.1 Thermal Effects 314
7.3.2 Noise Phenomena 314
7.3.3 Miscellaneous Issues 315
7.4 Low-Power Scan Testing 316
7.4.1 Basics of Scan Testing 316
7.4.2 ATPG and X-Filling Techniques 318
7.4.3 Low-Power Test Vector Compaction 320
7.4.4 Shift Control Techniques 321
7.4.5 Scan Cell Ordering 322
7.4.6 Scan Architecture Modification 324
7.4.7 Scan Clock Splitting 326
7.5 Low-Power Built-in Self-Test 328
7.5.1 Basics of Logic BIST 328
7.5.2 LFSR Tuning 329
7.5.3 Low-Power Test Pattern Generators 330
Contents xi
7.5.4 Vector Filtering BIST 331
7.5.5 Circuit Partitioning 332
7.5.6 Power-Aware Test Scheduling 334
7.6 Low-Power Test Data Compression 335
7.6.1 Coding-Based Schemes 336
7.6.2 Linear-Decompression-Based
Schemes 336
7.6.3 Broadcast-Scan-Based Schemes 337
7.7 Low-Power RAM Testing 339
7.8 Concluding Remarks 341
7.9 Exercises 342
Acknowledgments 344
References 344
8 Coping with Physical Failures, Soft Errors,
and Reliability Issues 351
Laung-Terng (L.-T.) Wang, Mehrdad Nourani, and T. M. Mak
8.1 Introduction 352
8.2 Signal Integrity 354
8.2.1 Basic Concept of Integrity Loss 354
8.2.2 Sources of Integrity Loss 356
8.2.2.1 Interconnects 356
8.2.2.2 Power Supply Noise 358
8.2.2.3 Process Variations 358
8.2.3 Integrity Loss Sensors/Monitors 360
8.2.3.1 Current Sensor 360
8.2.3.2 Power Supply Noise Monitor 361
8.2.3.3 Noise Detector (ND) Sensor 362
8.2.3.4 Integrity Loss Sensor (ILS) 362
8.2.3.5 Jitter Monitor 363
8.2.3.6 Process Variation Sensor 364
8.2.4 Readout Architectures 365
8.2.4.1 BIST-Based Architecture 365
8.2.4.2 Scan-Based Architecture 367
8.2.4.3 PV-Test Architecture 368
8.3 Manufacturing Defects, Process Variations, and.Reliability 370
8.3.1 Fault Detection 370
8.3.1.1 Structural Tests 371
8.3.1.2 Defect-Based Tests 372
8.3.1.3 Functional Tests 378
8.3.2 Reliability Stress 379
8.3.3 Redundancy and Memory Repair 381
8.3.4 Process Sensors and Adaptive Design 382
8.3.4.1 Process Variation Sensor 383
xii Contents
8.3.4.2 Thermal Sensor 383
8.3.4.3 Dynamic Voltage Scaling 385
8.4 Soft Errors 386
8.4.1 Sources of Soft Errors and SER Trends 387
8.4.2 Coping with Soft Errors 390
8.4.2.1 Fault Tolerance 390
8.4.2.2 Error-Resilient Microarchitectures 394
8.4.2.3 Soft Error Mitigation 398
8.5 Defect and Error Tolerance 402
8.5.1 Defect Tolerance 404
8.5.2 Error Tolerance 405
8.6 Concluding Remarks 407
8.7 Exercises 407
Acknowledgments 409
References 409
9 Design for Manufacturability and Yield 423
Robert C. Aitken
9.1 Introduction 423
9.2 Yield 426
9.3 Components of Yield 427
9.3.1 Yield Models 428
9.3.2 Yield and Repair 429
9.4 Photolithography 430
9.5 DFMandDFY 433
9.5.1 Photolithography 435
9.5.2 Critical Area 439
9.5.3 Yield Variation over Time 441
9.5.4 DFT and DFM/DFY 444
9.6 Variability 445
9.6.1 Sources of Variability 445
9.6.2 Deterministic versus Random Variability 446
9.6.3 Variability versus Defectivity 448
9.6.4 Putting It All Together 449
9.7 Metrics for DFX 449
9.7.1 The Ideal Case 450
9.7.2 Potential DFY Metrics 452
9.7.2.1 Critical Area 452
9.7.2.2 RET-Based Metrics 452
9.7.2.3 Example DRC-Based Metrics for DFM 454
9.8 Concluding Remarks 456
9.9 Exercises 457
Acknowledgments 458
References 459
Contents xiii
10 Design for Debug and Diagnosis 463
T. M. Mak and Srikanth Venkataraman
10.1 Introduction 463
10.1.1 What Are Debug and Diagnosis? 464
10.1.2 Where Is Diagnosis Used? 465
10.1.3 IC-Level Debug and Diagnosis 465
10.1.4 Silicon Debug versus Defect Diagnosis 466
10.1.5 Design for Debug and Diagnosis 467
10.2 Logic Design for Debug and Diagnosis
(DFD) Structures 468
10.2.1 Scan 468
10.2.2 Observation-Only Scan 469
10.2.3 Observation Points with Multiplexers 471
10.2.4 Array Dump and Trace Logic Analyzer 472
10.2.5 Clock Control 473
10.2.6 Partitioning, Isolation, and De-featuring 475
10.2.7 Reconfigurable Logic 476
10.3 Probing Technologies 476
10.3.1 Mechanical Probing 477
10.3.2 Injection-Based Probing 478
10.3.2.1 E-beam Probing 478
10.3.2.2 Laser Voltage Probing 479
10.3.3 Emission-Based Probing 483
10.3.3.1 Infrared Emission
Microscopy (IREM) 483
10.3.3.2 Picosecond Imaging Circuit
Analysis (PICA) 485
10.3.3.3 Time Resolved Emissions (TRE) 486
10.4 Circuit Editing 487
10.4.1 Focused Ion Beam 487
10.4.2 Layout-Database-Driven Navigation System 488
10.4.3 Spare Gates and Spare Wires 489
10.5 Physical DFD Structures 490
10.5.1 Physical DFD for Pico-Probing 490
10.5.2 Physical DFD for E-Beam 491
10.5.3 Physical DFD for FIB and Probing 492
10.6 Diagnosis and Debug Process 492
10.6.1 Diagnosis Techniques and Strategies 495
10.6.2 Silicon Debug Process and Flow 496
10.6.3 Debug Techniques and Methodology 497
10.7 Concluding Remarks 498
10.8 Exercises 499
Acknowledgments 500
References 500
xiv Contents
11 Software-Based Self-Testing 505
Jiun-Lang Huang and Kwang-Ting (Tim) Cheng
11.1 Introduction 506
11.2 Software-Based Self-Testing Paradigm 507
11.2.1 Self-Test Flow 508
11.2.2 Comparison with Structural BIST 509
11.3 Processor Functional Fault Self-Testing 510
11.3.1 Processor Model 510
11.3.2 Functional-Level Fault Models 512
11.3.3 Test Generation Procedures 513
11.3.3.1 Test Generation for Register
Decoding Fault 513
11.3.3.2 Test Generation for Instruction
Decoding and Control Fault 514
11.3.3.3 Test Generation for Data Transfer
and Storage Function 515
11.3.3.4 Test Generation for Data Manipulation
Function 516
11.3.3.5 Test Generation Complexity 516
11.4 Processor Structural Fault Self-Testing 516
11.4.1 Test Flow 516
11.4.1.1 Test Preparation 516
11.4.1.2 Self-Testing 517
11.4.2 Stuck-At Fault Testing 518
11.4.2.1 Instruction-Imposed I/O Constraint
Extraction 518
11.4.2.2 Constrained Component
Test Generation 519
11.4.2.3 Test Program Synthesis 521
11.4.2.4 Processor Self-Testing 522
11.4.3 Test Program Synthesis Using Virtual Constraint
Circuits (VCCs) 523
11.4.4 Delay Fault Testing 526
11.4.4.1 Functionally Untestable Delay Faults . 526
11.4.4.2 Constraint Extraction 527
11.4.4.3 Test Program Generation 528
11.4.5 Functional Random Instruction Testing 529
11.5 Processor Self-Diagnosis 530
11.5.1 Challenges to SBST-Based Processor Diagnosis 530
11.5.2 Diagnostic Test Program Generation 531
11.6 Testing Global Interconnect 533
11.6.1 Maximum Aggressor (MA) Fault Model 533
11.6.2 Processor-Based Address and Data Bus Testing 534
Contents xv
11.6.2.1 Data Bus Testing 534
11.6.2.2 Address Bus Testing 535
11.6.3 Processor-Based Functional MA Testing 536
11.7 Testing Nonprogrammable Cores 536
11.7.1 Preprocessing Phase 538
11.7.2 Core Test Phase 538
11.8 Instruction-Level DFT 538
11.8.1 Instruction-Level DFT Concept 538
11.8.2 Testability Instructions 539
11.8.3 Test Optimization Instructions 541
11.9 DSP-Based Analog/Mixed-Signal Component Testing 541
11.10 Concluding Remarks 543
11.11 Exercises 544
Acknowledgments 545
References 545
12 Field Programmable Gate Array Testing 549
Charles E. Stroud
12.1 Overview of FPGAs 549
12.1.1 Architecture 550
12.1.2 Configuration 554
12.1.3 The Testing Problem 556
12.2 Testing Approaches 558
12.2.1 External Testing and Built-in Self-Test 559
12.2.2 Online and Offline Testing 560
12.2.3 Application Dependent and Independent Testing . 561
12.3 BIST of Programmable Resources 562
12.3.1 Logic Resources 563
12.3.1.1 Programmable Logic Blocks 567
12.3.1.2 Input/Output Cells 570
12.3.1.3 Specialized Cores 571
12.3.1.4 Diagnosis 575
12.3.2 Interconnect Resources 578
12.4 Embedded Processor-Based Testing 583
12.5 Concluding Remarks 585
12.6 Exercises 586
Acknowledgments 587
References 587
13 MEMS Testing 59^1
Ramesh Ramadoss, Robert Dean, and Xingguo Xiong
13.1 Introduction 592
13.2 MEMS Testing Considerations 593
xvi Contents
13.3 Test Methods and Instrumentation for MEMS 594
13.3.1 Electrical Test 595
13.3.2 Optical Test Methods 596
13.3.3 Material Property Measurements 598
13.3.4 Failure Modes and Analysis 599
13.3.5 Mechanical Test Methods 600
13.3.6 Environmental Testing 607
13.4 RF MEMS Devices 609
13.4.1 RF MEMS Switches 610
13.4.2 RF MEMS Resonators 611
13.5 Optical MEMS Devices 614
13.6 Fluidic MEMS Devices 616
13.6.1 MEMS Pressure Sensor 617
13.6.2 MEMS Humidity Sensor 618
13.7 Dynamic MEMS Devices 620
13.7.1 MEMS Microphone 620
13.7.2 MEMS Accelerometer 621
13.7.3 MEMS Gyroscope 622
13.8 Testing Digital Microfluidic Biochips 625
13.8.1 Overview of Digital Microfluidic Biochips 626
13.8.2 Fault Modeling 627
13.8.3 Test Techniques 628
13.8.4 Application to a Fabricated Biochip 631
13.9 DFT and BIST for MEMS 633
13.9.1 Overview of DFT and BIST Techniques 633
13.9.2 MEMS BIST Examples 637
13.10 Concluding Remarks 643
13.11 Exercises 644
Acknowledgments 646
References 646
14 High-Speed I/O Interfaces 653
Mike Peng Li, T. M. Mak, and Kwang-Ting (Tim) Cheng
14.1 Introduction 654
14.2 High-Speed I/O Architectures 657
14.2.1 Global Clock I/O Architectures 657
14.2.2 Source Synchronous I/O Architectures 658
14.2.3 Embedded Clock I/O Architectures 660
14.2.3.1 Jitter Components 661
14.2.3.2 Jitter Separation 662
14.2.3.3 Jitter, Noise, and Bit-Error-Rate
Interactions 666
14.3 Testing of I/O Interfaces 668
14.3.1 Testing of Global Clock I/O 669
Contents xvii
14.3.2 Testing of Source Synchronous I/O 669
14.3.3 Testing of Embedded Clock High-Speed Serial I/O . 671
14.3.3.1 Transmitter 671
14.3.3.2 Channel or Medium 673
14.3.3.3 Receiver 675
14.3.3.4 Reference Clock 677
14.3.3.5 System-Level Bit-Error-Rate
Estimation 678
14.3.3.6 Tester Apparatus Considerations 678
14.4 DFT-Assisted Testing 680
14.4.1 AC Loopback Testing 681
14.4.2 High-Speed Serial-Link Loopback Testing 683
14.4.3 Testing the Equalizers 686
14.5 System-Level Interconnect Testing 690
14.5.1 Interconnect Testing with Boundary Scan 690
14.5.2 Interconnect Testing with High-Speed
Boundary Scan 691
14.5.3 Interconnect Built-in Self-Test 693
14.6 Future Challenges 694
14.7 Concluding Remarks 695
14.8 Exercises 696
Acknowledgments 697
References 697
15 Analog and Mixed-Signal Test Architectures 703
F. Foster Dai and Charles E. Stroud
15.1 Introduction 704
15.2 Analog Functional Testing 705
15.2.1 Frequency Response Testing 705
15.2.2 Linearity Testing 707
15.2.3 Signal-to-Noise Ratio Testing 709
15.2.4 Quantization Noise 710
15.2.5 Phase Noise 712
15.2.6 Noise in Phase-Locked Loops 715
15.2.6.1 In-Band PLL Phase Noise 716
15.2.6.2 Out-Band PLL Phase Noise 718
15.2.6.3 Optimal Loop Setting 718
15.2.7 DAC Nonlinearity Testing 719
15.3 Analog and Mixed-Signal Test Architectures 720
15.4 Defect-Oriented Mixed-Signal BIST Approaches 724
15.5 FFT-Based Mixed-Signal BIST 727
15.5.1 FFT 727
15.5.2 Inverse FFT 729
15.5.3 FFT-Based BIST Architecture 729
xviii Contents
15.5.4 FFT-Based Output Response Analysis 730
15.5.5 FFT-Based Test Pattern Generation 731
15.6 Direct Digital Synthesis BIST 733
15.6.1 DDS-Based BIST Architecture 734
15.6.2 Frequency Response Test and Measurement 736
15.6.3 Linearity Test and Measurement 738
15.6.4 SNR and Noise Figure Measurement 739
15.7 Concluding Remarks 739
15.8 Exercises 740
Acknowledgments 741
References 741
16 RF Testing 745
Soumendu Bhattacharya and Abhijit Chatterjee
16.1 Introduction 746
16.1.1 RF Basics 746
16.1.2 RF Applications 748
16.2 Key Specifications for RF Systems 750
16.2.1 Test Instrumentation 750
16.2.1.1 Spectrum Analyzer 751
16.2.1.2 Network Analyzer 752
16.2.1.3 Noise Figure Meter 753
16.2.1.4 Phase Meter 755
16.2.2 Test Flow in Industry 755
16.2.2.1 Design and Fabrication 756
16.2.2.2 Characterization Test 756
16.2.2.3 Production Test 756
16.2.3 Characterization Test and Production Test 757
16.2.3.1 Accuracy 757
16.2.3.2 Time Required for Testing 758
16.2.3.3 Cost of Testing 758
16.2.4 Circuit-Level Specifications 758
16.2.4.1 Gain 759
16.2.4.2 Harmonics and Third-Order
Intercept Point (IP3) 759
16.2.4.3 1-dB Compression Point (P_ldB) 763
16.2.4.4 Total Harmonic Distortion (THD) 763
16.2.4.5 Gain Flatness 764
16.2.4.6 Noise Figure 765
16.2.4.7 Sensitivity and Dynamic Range 767
16.2.4.8 Local Oscillator Leakage 768
16.2.4.9 Phase Noise 768
16.2.4.10 Adjacent Channel Power Ratio 769
Contents xix
16.2.5 System-Level Specifications 770
16.2.5.1 I-Q Mismatch 770
16.2.5.2 Error Vector Magnitude 771
16.2.5.3 Modulation Error Ratio 772
16.2.5.4 Bit Error Rate 773
16.2.6 Structure of RF Systems 774
16.3 Test Hardware: Tester and DIB/PIB 776
16.4 Repeatability and Accuracy 779
16.5 Industry Practices for High-Volume Manufacturing 782
16.5.1 Test Cost Analysis 783
16.5.2 Key Trends 784
16.6 Concluding Remarks 785
16.7 Exercises 786
Acknowledgments 787
References 788
17 Testing Aspects of Nanotechnology Trends 791
Mehdi B. Tahoori, Niraj K. Jha, and R. Iris Bahar
17.1 Introduction 792
17.2 Resonant Tunneling Diodes and Quantum-Dot
Cellular Automata 794
17.2.1 Testing Threshold Networks with Application
toRTDs 795
17.2.2 Testing Majority Networks with Application
toQCA 799
17.3 Crossbar Array Architectures 807
17.3.1 Hybrid Nanoscale/CMOS Structures 810
17.3.1.1 ThenanoPLA 810
17.3.1.2 Molecular CMOS (CMOL) 813
17.3.2 Built-in Self-Test 815
17.3.3 Simultaneous Configuration and Test 817
17.4 Carbon Nanotube (CNT) Field Effect Transistors 820
17.4.1 Imperfection-Immune Circuits for
Misaligned CNTs 820
17.4.2 Robust Circuits for Metallic CNTs 824
17.5 Concluding Remarks 826
Acknowledgments 826
References 827
Index 833 |
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| genre_facet | Patentschrift |
| id | DE-604.BV023290696 |
| illustrated | Illustrated |
| index_date | 2024-07-02T20:43:07Z |
| indexdate | 2024-07-09T21:15:05Z |
| institution | BVB |
| isbn | 012373973X 9780123739735 |
| language | English |
| lccn | 2007023373 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-016475315 |
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| physical | XXXVI, 856 S. Ill., zahlr. graph. Darst. 24 cm |
| publishDate | 2008 |
| publishDateSearch | 2008 |
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| publisher | Elsevier/Morgan Kaufmann Publ. |
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| series2 | The Morgan Kaufmann series in systems on silicon |
| spelling | System-on-chip test architectures nanometer design for testability ed. by Laung-Terng Wang ; Charles Stroud ; Nur A. Touba Amsterdam [u.a.] Elsevier/Morgan Kaufmann Publ. 2008 XXXVI, 856 S. Ill., zahlr. graph. Darst. 24 cm txt rdacontent n rdamedia nc rdacarrier The Morgan Kaufmann series in systems on silicon Literaturangaben Systems on a chip / Testing Integrated circuits / Very large scale integration / Testing Integrated circuits / Very large scale integration / Design Integrated circuits Very large scale integration Design Integrated circuits Very large scale integration Testing Systems on a chip Testing VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)4173536-5 Patentschrift gnd-content VLSI (DE-588)4117388-0 s DE-604 Wang, Laung-Terng Sonstige oth Stroud, Charles E. Sonstige oth http://catdir.loc.gov/catdir/toc/ecip0719/2007023373.html Inhaltsverzeichnis http://catdir.loc.gov/catdir/enhancements/fy0808/2007023373-d.html Beschreibung für Leser http://www.loc.gov/catdir/toc/ecip0719/2007023373.html Table of contents only lizenzfrei http://www.loc.gov/catdir/enhancements/fy0808/2007023373-d.html Publisher description lizenzfrei HBZ Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016475315&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | System-on-chip test architectures nanometer design for testability Systems on a chip / Testing Integrated circuits / Very large scale integration / Testing Integrated circuits / Very large scale integration / Design Integrated circuits Very large scale integration Design Integrated circuits Very large scale integration Testing Systems on a chip Testing VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4173536-5 |
| title | System-on-chip test architectures nanometer design for testability |
| title_auth | System-on-chip test architectures nanometer design for testability |
| title_exact_search | System-on-chip test architectures nanometer design for testability |
| title_exact_search_txtP | System-on-chip test architectures nanometer design for testability |
| title_full | System-on-chip test architectures nanometer design for testability ed. by Laung-Terng Wang ; Charles Stroud ; Nur A. Touba |
| title_fullStr | System-on-chip test architectures nanometer design for testability ed. by Laung-Terng Wang ; Charles Stroud ; Nur A. Touba |
| title_full_unstemmed | System-on-chip test architectures nanometer design for testability ed. by Laung-Terng Wang ; Charles Stroud ; Nur A. Touba |
| title_short | System-on-chip test architectures |
| title_sort | system on chip test architectures nanometer design for testability |
| title_sub | nanometer design for testability |
| topic | Systems on a chip / Testing Integrated circuits / Very large scale integration / Testing Integrated circuits / Very large scale integration / Design Integrated circuits Very large scale integration Design Integrated circuits Very large scale integration Testing Systems on a chip Testing VLSI (DE-588)4117388-0 gnd |
| topic_facet | Systems on a chip / Testing Integrated circuits / Very large scale integration / Testing Integrated circuits / Very large scale integration / Design Integrated circuits Very large scale integration Design Integrated circuits Very large scale integration Testing Systems on a chip Testing VLSI Patentschrift |
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