Low-complexity architecture for AR(1) inference

In this Letter, the authors propose a low-complexity estimator for the correlation coefficient based on the signed $\operatorname {\rm AR}\lpar 1\rpar $AR⁡(1) process. The introduced approximation is suitable for implementation in low-power hardware architectures. Monte Carlo simulations reveal that...

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Veröffentlicht in:Electronics letters 2020-07, Vol.56 (14), p.732-734
Hauptverfasser: Borges, A, Cintra, R.J, Coelho, D.F.G, Dimitrov, V.S
Format: Artikel
Sprache:eng
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Zusammenfassung:In this Letter, the authors propose a low-complexity estimator for the correlation coefficient based on the signed $\operatorname {\rm AR}\lpar 1\rpar $AR⁡(1) process. The introduced approximation is suitable for implementation in low-power hardware architectures. Monte Carlo simulations reveal that the proposed estimator performs comparably to the competing methods in the literature with maximum error in order of $10^{-2}$10−2. However, the hardware implementation of the introduced method presents considerable advantages in several relevant metrics, offering more than 95% reduction in dynamic power and doubling the maximum operating frequency when compared to the reference method.
ISSN:0013-5194
1350-911X
1350-911X
DOI:10.1049/el.2019.4030