Yield estimation model for lithography hotspot distortions

A yield formulation model to estimate the amount of lithography distortion expected in a printed layout is proposed. The yield formulation relates the probability of non-failure of a lithography hotspot with the yield loss. The application of the yield model is demonstrated for three different layou...

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Veröffentlicht in:	Electronics letters 2013-08, Vol.49 (17), p.1066-1068
Hauptverfasser:	Gómez, S, Moll, F
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Circuits and systems distortion Electronics Enginyeria dels materials Enginyeria electrònica Exact sciences and technology failure analysis Hot spot Inventory control, production control. Distribution lithography lithography hotspot distortion Litografia Litografia per feix d'electrons losses Manufacturing yield manufacturing yield improvement Microelectronic fabrication (materials and surfaces technology) nonfailure analysis Operational research and scientific management Operational research. Management science printed layout probability Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices unidimensional design Yield estimation yield estimation model Yield loss Yield modeling Àrees temàtiques de la UPC
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Beschreibung
Zusammenfassung:	A yield formulation model to estimate the amount of lithography distortion expected in a printed layout is proposed. The yield formulation relates the probability of non-failure of a lithography hotspot with the yield loss. The application of the yield model is demonstrated for three different layout configurations showing that unidimensional designs may improve manufacturing yield.
ISSN:	0013-5194 1350-911X 1350-911X
DOI:	10.1049/el.2013.0469