Reduction of the Hysteresis Voltage in Atomic‐Layer‐Deposited p‐Type SnO Thin‐Film Transistors by Adopting an Al2O3 Interfacial Layer

The origin of hysteresis in the drain–source current (IDS)–gate‐source voltage (VGS) characteristics of atomic‐layer‐deposited (ALD) p‐type SnO thin‐film transistors (TFTs) is examined by adding ALD Al2O3 interfacial layers (IL) between the SnO channel layer and the SiO2 gate insulator (GI) layer. SnO TFTs with SiO2 GI exhibit a large hysteresis voltage (Vhy) due to the trap state density near the interface between the SnO active layer and the SiO2 GI (known as the border trap). Both experimental results and theoretical calculations show that the origin of border traps is the SnSi+0 gap states in SiO2, which is induced by the Sn diffusion into the SiO2 layer. The use of Al2O3 films as ILs suppresses this diffusion. The effectiveness, however, is dependent on the thickness, crystallinity, and density of the Al2O3 films. The Vhy of the SnO TFTs can be decreased when the thickness and density of the ILs is increased if the amorphous structure of the Al2O3 IL is maintained after the rapid thermal annealing process. p‐Type ALD SnO TFTs with optimum ILs exhibit a high on‐off ratio of IDS (1.2 × 105), high field‐effect mobility (1.6 cm2 V−1 s−1), and a small Vhy (0.2 V). Atomic‐layer‐deposited (ALD) p‐type SnO thin‐film transistors (TFTs) are fabricated. The use of an Al2O3 interfacial layer (IL) in the ALD decreases the hysteresis voltage, as Al2O3 film suppresses Sn diffusion into the SiO2 gate insulator layer. The efficiency is further promoted by rapid thermal annealing of the IL.