Embedded Wafer‐Level Ball Grid Array (eWLB) Packaging Technology Platform

Wafer‐level packaging (WLP) is one of the fastest‐growing packaging technologies on the market today. Fan‐out WLP (FO‐WLP) is the extension of WLP and provides higher input and output (I/O) capability. The version of FO‐WLP technology reviewed in this chapter is called embedded wafer‐level ball grid array (eWLB). Chip‐first technology can be distinguished in two different categories: die face‐down or die face‐up assembly approach during the construction of the molded wafer, also called the reconstituted wafer. The electrical performance of FO‐WLP generally is very good because of short, low resistance connections and very low parasitics. The chapter compares the warpage behavior and the electrical and thermal performance of different package platforms. The proof of electrical functionality is an important milestone for any package platform. Chip scale packages (CSP) are tested after singulation into discrete packages. FO‐WLP can also be tested after package singulation like CSP.