A Dual-Channel High-Linearity Filtering-by-Aliasing Receiver Front-End Supporting Carrier Aggregation

A filtering-by-aliasing (FA) receiver front-end based on a slice-based time-varying architecture was described by Bu and Pamarti (2021). Unlike prior FA architectures, it demonstrated, using a 28-nm CMOS prototype IC, a time-invariant input impedance that enables dual-channel operation with high linearity. Up to 50-dB stopband rejection with a transition bandwidth (BW) of only 3.2 times the RF BW, out-of-band IIP 3 of +35 dBm, blocker 1-dB compression point of +12 dBm, and local oscillator (LO) leakage power better than −81 dBm were achieved, using a 0.9-V supply. This article elaborates on the design of this prototype, presents detailed analyses of the slice-based architecture, and shows how it addresses many of the prior FA receivers' problems.