A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (V-BB) with high pumping efficiency at a low supply voltage (V-DD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level vertical bar V-BB vertical bar, and small pumping currents at very low V-DD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to V-DD = 0.4 V, and vertical bar V-BB vertical bar/V-DD is obtained to be 86.1% at V-DD = 0.5 V and C-load = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at V-DD = 0.6 V and R-L = 10 K Omega, and the pumping current is 2.17 times greater at V-DD = 1.2 V and V-BB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.