Positive bias temperature instability of HfO2-based gate stacks at reduced thermal budget for future CMOS technologies

CMOS technology has always exploited the high thermal stability of Si, which enables high temperature fabrication steps for various device improvements, in particular, for curing oxide defects and hence improving the device stability and reliability. However, with the rise of novel device and architecture concepts such as sequential 3D stacking of Si CMOS tiers in a monolithic integration flow, or the introduction of high-mobility Ge/III–V channels, this paradigm cannot be maintained, and the entire fabrication flow will have to be enabled at a reduced thermal budget. We investigate the current industry standard high-k dielectric, HfO2, showing how its charge trapping behavior evolves when reducing the overall fabrication thermal budget, affecting the positive bias temperature instability (PBTI) of the device. We perform this study focusing on thermal budget ranges of relevance for gate stack development compatible with future technologies. Our finding of reduced reliability at lower thermal budgets (especially 400 °C, oxygen vacancies might become the dominant species.