Design for Stuck-at Fault Testability in Toffoli–Fredkin Reversible Circuits

An intense trade-off arises between testing, hardware and speed of electronic circuits. An efficient design for testability methodology for the detection of stuck-at faults in reversible circuits is presented in this paper by exploiting the properties of Toffoli and Fredkin gates. An ( n + 1 ) dimensional general test set depicted in the paper is found complete for the detection of single and multiple stuck-at faults in the modified circuit. A set of benchmark circuits are taken for experimentation where the proposed work achieved a reduction up to 25.0 % in gate cost and 35.8 % in quantum cost when compared to the existing work of the area that proves its efficacy towards the reduction in hardware cost with limited degradation in speed.