A low sampling clock, high bandwidth, master‐slave track and hold amplifier

A low sampling clock, high bandwidth, master‐slave track and hold amplifier

A fully‐differential master‐slave track and hold amplifier (MSTHA), with one‐input, four‐output and nearly 20 GHz bandwidth is designed and fabricated in 0.13‐μm SiGe BiCMOS technology. Operating with a single +3.3 V supply, 0 V input direct‐voltage, 2 GHz sampling clock input and 5 dBm input power,...

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Veröffentlicht in:International journal of RF and microwave computer-aided engineering 2020-01, Vol.30 (1), p.n/a, Article 22005
Hauptverfasser: Zhang, Guifu, Zhou, Jie, Liu, Youjiang, Cao, Tao, Qiu, Yongtao, Li, Biao
Format: Artikel
Sprache:eng
Schlagworte:
Amplifiers
bandwidth
Computer Science
Computer Science, Interdisciplinary Applications
Engineering
Engineering, Electrical & Electronic
master‐slave
MSTHA
Noise levels
Power consumption
Sampling
Science & Technology
SFDR
SiGe BiCMOS
Technology
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Beschreibung
Zusammenfassung:A fully‐differential master‐slave track and hold amplifier (MSTHA), with one‐input, four‐output and nearly 20 GHz bandwidth is designed and fabricated in 0.13‐μm SiGe BiCMOS technology. Operating with a single +3.3 V supply, 0 V input direct‐voltage, 2 GHz sampling clock input and 5 dBm input power, the MSTHA achieves a spurious free dynamic range (SFDR) of less than −31 dB up to 20 GHz, 0.5 mVrms output noise amplitude (RMS, root of mean square) and totally power consuming about 1.3 W.
ISSN:1096-4290
1099-047X
DOI:10.1002/mmce.22005