A NEW APPROACH TO PROGRAMMABLE LOGIC ARRAY FOR SINGLE-CLOCK CMOS

Programmable Logic Array （PLA） is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Combining both dynamic and static design style rather than introducing additional interface-buffers overcomes the racing problem, thereby saves the chip area. Besides inheriting the advantages of dynamic circuit--low power dissipation and compact structure, this approach also provides high-speed operation.