Comparison of combinational and sequential error rates and a low overhead technique for single event transient mitigation

Single Event Effects (SEE) in combinational logic circuits, caused due radiation particle strikes are a major concern for modern high-speed devices. The frequency dependence of SEE in state-of-the-art 40 nm circuits is evaluated and the contribution of logic errors to the chip-level Soft Error Rate (SER) is quantified experimentally. A model is developed to help predict the frequency threshold at which logic errors could dominate the chip-level SER. Results suggest that, due to higher transistor density and higher operating frequencies, logic soft errors could exceed the flip-flop error rate for future technologies. A low overhead probabilistic technique to harden logic circuits against radiation induced errors is also developed.