Validation of Cycle-Accurate CPU Simulators against Real Hardware

One of the most important issues regarding real-time software performance is the worst case execution time (WCET). There are several methods for deducing the WCET statically; one such analysis system is currently under development by WCET researchers from Uppsala University in co-operation with C-lab in Paderborn. The system uses a CPU simulator for calculating the execution time of selected parts of the target program, which creates a demand for a very cycle-accurate simulator. In this thesis, we give a method for validating a CPU simulator against real hardware CPU. The proposed test method is a black-box test method that relies on hardware analysis for test-case generation. The validation method aims at both determining the accuracy of the simulator and to pinpoint simulator errors for improving the accuracy. We have tested this validation method on a NEC V850 CPU core simulator, and the results show that the average error-rate drops from 11,2% to 1,3% for a set of benchmark programs. Note: M.Sc. thesis