Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors

In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.