High speed multiple memory interface I/O cell

High speed multiple memory interface I/O cell

An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

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Bibliographische Detailangaben
Hauptverfasser: Bhakta, Dharmesh, Lim, Hong-Him, Kong, Cheng-Gang, Randazzo, Todd
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.