Fault modeling for state retention logic

A method for modeling state-retention logic includes: specifying a circuit that includes an arrangement of circuit elements, wherein a portion of the circuit is organized into a power domain with a power-domain control for effecting power variations within the power domain, and the power domain incl...

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Bibliographische Detailangaben

Hauptverfasser:	Chakravadhanula, Krishna, Gregor, Steven L, Keller, Brion L, Chickermane, Vivek
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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