Memory test circuit, semiconductor integrated circuit and memory test method

A memory test circuit tests a memory including an actual array portion and a redundancy portion. The memory test circuit includes: an input data selector outputting first test data excluding data for the redundancy portion in test data representing data for the actual array portion and the redundancy portion as input selecting data in a redundancy BIST mode (RBM); an input data switching circuit outputting the test data as output test data to the memory in a direct BIST mode (DBM), and outputting data obtained by adding redundancy bits to the input selecting data as the output test data to the memory based on the input selecting data and output redundancy codes representing redundancy codes in the RBM; an output data switching circuit outputting data obtained by removing the redundancy bits from read data as output selecting data based on the read data from the memory and the output redundancy codes in the RBM; and a memory BIST comparator checking a value of the read data with a checking expectation value to output a checking result as a test result in the DBM, and checking a value of the output selecting data with an expectation value for the actual array portion in the checking expectation value to output a checking result as the test result in the RBM.