Method and apparatus for performing lutmask based delay modeling

Method and apparatus for performing lutmask based delay modeling

A method for determining a delay through a lookup table (LUT) in a logic array block (LAB) of a field programmable gate array (FPGA) for a signal includes identifying paths through the LUT that are taken for the signal. Delays are computed for the signal only on the paths identified.

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Bibliographische Detailangaben
Hauptverfasser: Oh, Jungmoo, Carvalho, Lyndon Francis, Wysocki, Chris
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A method for determining a delay through a lookup table (LUT) in a logic array block (LAB) of a field programmable gate array (FPGA) for a signal includes identifying paths through the LUT that are taken for the signal. Delays are computed for the signal only on the paths identified.