Parallel memory device rank selection

Parallel memory device rank selection

A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dua...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Warnes, Lidia, Lee, Teddy, Espinoza-Ibarra, Ricardo Ernesto, Carr, Dennis, Calhoun, Michael Bozich
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules).