System and method for providing alignment mark for high-k metal gate process

System and method for providing alignment mark for high-k metal gate process

The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a substrate having a device region and an alignment region; a first shallow trench isolation (STI) feature in the alignment region and having a first depth D; a second STI feature i...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Chen, Kuei Shun, Chen, Meng-Wei, Liu, George, Huang, Jiann Yuan, Lin, Chia-Ching
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a substrate having a device region and an alignment region; a first shallow trench isolation (STI) feature in the alignment region and having a first depth D; a second STI feature in the device region and having a second depth D; an alignment mark with patterned features overlying the first STI in the alignment region; and a gate stack formed on an active region in the device region.