Digital-analog converter

In order to reduce a current mismatch by laying-out the bias circuit of current cells adjacent to each other in a common current centroid manner or connecting the output lines of the current cells in a tournament manner, there is provided a digital-analog converter in which a plurality of current cells are two dimensionally and symmetrically disposed according to a previously determined order, the digital-analog converter including: a first current cell group including a portion of the plurality of current cells; and a second current cell group including the rest of the plurality of current cells, not included in the first current cell group, the outputs of each current cell of the first current cell group being connected to the outputs of each current cell of the second current cell group in a tournament manner, wherein each of the plurality of current cells includes: a switch circuit switching the output and block of a unit current according to an input signal; and a bias circuit mirroring current supplied according to the switching of the switch circuit and converting the current into the unit current, the bias circuit of two current cells adjacent to each other among the plurality of current cells being laid-out in a common current centroid manner.