Table-based DFM for accurate post-layout analysis

Table-based DFM for accurate post-layout analysis

Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of th...

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Bibliographische Detailangaben
Hauptverfasser: Hou, Yung-Chin, Cheng, Ying-Chou, Liu, Ru-Gun, Lai, Chih-Ming, Cheng, Yi-Kan, Lin, Chung-Kai, Chao, Hsiao-Shu, Yeh, Ping-Heng, Wu, Min-Hong, Ku, Yao-Ching, Ou, Tsong-Hua
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.