Integrated circuit having interleaved gridded features, mask set and method for printing

A method for fabricating an integrated circuit includes the step of providing a substrate having a semiconductor surface. For at least one masking level (e.g. gate electrode, contact or via) of the integrated circuit, a mask pattern for the masking level is partitioned into a first mask and at least a second mask. The first mask provides features in a first grid pattern and the second mask provides features in a second grid pattern. The first and second grid pattern have respective features that interleave with one another over at least one area. A first photoresist film is applied onto the surface of the substrate. The first grid pattern is printed using the first mask. The second grid pattern is printed using the second mask. The first and said second grid pattern are then etched into the surface of the substrate. Another embodiment of the invention includes an integrated circuit that has vias or contacts in a grid-like feature pattern in at least one multi-transistor area of the circuit including at least 5 transistors, wherein a minimum horizontal or minimum vertical center-to-center spacing distance between neighboring features in the pattern is ≦100 nm.