Test circuit for measuring resistance distribution of memory cells and semiconductor system including the same

The test circuit for measuring a resistance distribution of memory cells includes a sensing circuit and a digital value generation circuit. The sensing circuit compares a reference voltage with a voltage of a sensing node receiving a voltage of a bit line connected with a resistive element and generates a sensing signal. The digital value generation circuit generates a digital value corresponding to a resistance-capacitance (RC) delay of the bit line in response to the sensing signal from the sensing circuit.