Methods and apparatus for estimating a position of a stuck-at defect in a scan chain of a device under test

As a scan pattern is shifted out of a scan chain, the scan pattern is evaluated in real-time for the existence of a logic condition. A reference to a portion of the scan pattern that is currently being evaluated is maintained. Upon identifying the existence of the logic condition when the reference...

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Bibliographische Detailangaben
Hauptverfasser: Burlison, Phillip D, Frediani, John K
Format: Patent
Sprache:eng
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Zusammenfassung:As a scan pattern is shifted out of a scan chain, the scan pattern is evaluated in real-time for the existence of a logic condition. A reference to a portion of the scan pattern that is currently being evaluated is maintained. Upon identifying the existence of the logic condition when the reference has a predetermined relationship to a stored value, the stored value is overwritten using the reference. The stored value is then used to estimate the position of a stuck-at defect in the scan chain.