Tracking circuit for reducing faults in a memory

A memory circuit includes a plurality of memory cells and a plurality of bit lines and row lines connected to the memory cells for accessing selected memory cells. The memory circuit includes a programmable voltage source adapted for connection to at least one bit line and operative to precharge the bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the bit line. A control circuit coupled to the bit line is operative to oppose discharge of the bit line during at least a portion of a given memory read cycle. A tracking circuit connected to the control circuit is operative to control a delay in activation of the control circuit and/or a duration of time the control circuit is active as a function of a parameter affecting signal development time of a data signal on the bit line.