Capacitor arrangement method and layout apparatus

A layout apparatus stores a plurality of capacitor cells which are classifiable into a first classification for identifying capacitor cells having different sizes by frequency characteristic correlating with gate width of a capacitor and a second classification for identifying capacitor cells having...

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Bibliographische Detailangaben
1. Verfasser: Uchida, Kohei
Format: Patent
Sprache:eng
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Zusammenfassung:A layout apparatus stores a plurality of capacitor cells which are classifiable into a first classification for identifying capacitor cells having different sizes by frequency characteristic correlating with gate width of a capacitor and a second classification for identifying capacitor cells having different frequency characteristics by cell size. The layout apparatus: recognizes a plurality of combinations of a directed frequency characteristic and arrangement area; selects, for each of the combinations, capacitor cells corresponding to the directed frequency characteristic based on the first classification; reads out the capacitor cells in the descending order of cell size from the selected capacitor cells; arranges the read out capacitor cells to fill the directed arrangement area; checks a violation of capacitor density for all the directed arrangement areas of the plurality of combinations; replaces, when detecting the violation, a capacitor cell having larger gate width out of the arranged capacitor cells with a capacitor cell having smaller gate width besides the same cell size as the capacitor cell having larger gate width in accordance with the second classification; and retries checking the violation of capacitor density after finishing the replacement.