Color sequential timing controlling circuit and both color sequential display system and method thereof

In a line data sorting unit of a color sequential timing controlling circuit, inputted pixels/sub-pixels are buffered, sorted, and outputted. The pixels/sub-pixels are also sorted by a color data sorting unit according to the color sequential method and colors of sub-pixels so that a driving controller writes sorted sub-pixels of various colors onto a display panel within a short time variation to generate a full-color frame. The line data sorting unit buffers pixels/sub-pixels as a matrix, and loads the buffered pixels/sub-pixels line-by-line with respect to the matrix, where the pixels/sub-pixels are arranged and read in parallel according to sizes of lines of the matrix and a number of simultaneously-activated gate lines of a scanning driver.