Error correction for digital systems

An interface system is provided between a source component and a destination component having multiple parallel lines for transmitting data or parity bits (--) and one or more spare lines (-). An error detection means identifies one or more faulty lines. A mapping means re-routes data or parity from a faulty line to a spare line. A communication link is provided for communicating the re-routing between the source component and the destination component. The error detection and mapping can be repeated to detect and re-route sequential multiple-bit line errors using additional spare lines (-).