Stackable semiconductor device packages including openings partially exposing connecting elements, conductive bumps, or conductive conductors

CU UCIn one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width W, and at least one of the openings has a width Wadjacent to an upper surface of the package body, such that W>W.