Threshold dithering for time-to-digital converters

Techniques for dithering quantization thresholds of time-to-digital converters (TDC's) in all-digital phase-locked loops (ADPLL's) are disclosed. In an embodiment, the delay introduced by an individual buffer in a TDC delay line may be dithered. In another embodiment, the delay associated with the TDC delay line may be extended by a fixed amount to accommodate dithering of the zero-delay threshold.