Bit ordering for packetised serial data transmission on an integrated circuit
An on-chip integrated circuit interconnect uses a serialization technique to divide a transaction to be transmitted into a sequence of transmission packets which are serially transmitted over a narrower connection. The order in which bits of the transaction are allocated to transmission packets is s...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | An on-chip integrated circuit interconnect uses a serialization technique to divide a transaction to be transmitted into a sequence of transmission packets which are serially transmitted over a narrower connection. The order in which bits of the transaction are allocated to transmission packets is selected such that higher priority bits required by a receiving slave device in order that it can commence processing the transaction are sent first. This reduces the latency of the system. |
---|