Performance monitoring device and method thereof

A performance monitoring device and method are disclosed. The device monitors performance events of a processor. A counter is adjusted in response to the occurrence of a particular performance event. The counter can be associated with a particular instruction address range, or a data address range, so that the counter is adjusted only when the performance event occurs at the instruction address range or the data address range. Accordingly, the information stored in the counter can be analyzed to determine if a particular instruction address range or data address range results in a particular performance event. Multiple counters, each associated with a different performance event, instruction address range, or data address range, can be employed to allow for a detailed analysis of which portions of a program lead to particular performance events.