Techniques for integrated circuit clock management using multiple clock generators

A clock generator system includes a phase locked loop (PLL), a first clock generator, and a second clock generator. The PLL includes a first output configured to provide a first clock signal at a first frequency and a second output configured to provide a second clock signal at the first frequency. The second clock signal is out-of-phase with the first clock signal. An output of the first clock generator is configured to provide a first generated clock signal whose effective frequency is based on both the first and second clock signals and a first mode signal. An output of the second clock generator is configured to provide a second generated clock signal whose effective frequency is based on both the first and second clock signals and a second mode signal.