Memory interface circuit and memory system including the same

The memory interface circuit may include a master delay unit and a slave delay unit. The master delay unit generates a control signal for controlling a delay time based on a clock signal. The slave delay unit selects one signal of an inversion signal of the clock signal and a data strobe signal in response to a mode signal and delays the selected signal in response to the control signal. The slave delay unit selectively outputs a delayed clock signal that may be delayed by a first phase with respect to the clock signal or a delayed data strobe signal that may be delayed by a second phase with respect to the data strobe signal.