Attaching and virtualizing reconfigurable logic units to a processor

In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and back-end stages, and the execution units are coupled between dispatch ports of the front-end stages and writeback ports of the back-end sta...

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Bibliographische Detailangaben
1. Verfasser: Glew, Andrew F
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
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