Attaching and virtualizing reconfigurable logic units to a processor

In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and back-end stages, and the execution units are coupled between dispatch ports of the front-end stages and writeback ports of the back-end stages. Further, a reconfigurable logic is coupled between one of the dispatch ports and one of the writeback ports to perform specialized operations or handle instructions that are not part of an instruction set architecture (ISA) used by the pipeline. Other embodiments are described and claimed.