Logic non-volatile memory cell with improved data retention ability

A memory cell includes a semiconductor substrate; and a first, a second, and a third transistor. The first transistor includes a first dielectric over the semiconductor substrate; and a first floating gate over the first dielectric. The second transistor is electrically coupled to the first transistor and includes a second dielectric over the semiconductor substrate; and a second floating gate over the second dielectric. The first and the second floating gates are electrically disconnected. The memory cell further includes a first capacitor; a second capacitor electrically coupled to the first capacitor; a third capacitor; a fourth capacitor electrically coupled to the third capacitor, wherein each of the first, the second, the third and the fourth capacitors includes the semiconductor substrate as one of the capacitor plates. The third transistor is a selector of the memory cell and is electrically coupled to the first and the second transistors.