Image signal processor and method for outputting deferred vertical synchronous signal

th A method of transferring a deferred vertical synchronous signal and an image signal processor executing the method thereof are disclosed. Once the vertical synchronous signal for an mframe is inputted from an encoding unit, the method monitors whether image data columns in the quantity of n corresponding to a predetermined process block have been stored, using a count value inputted from the encoding unit, and outputs a corresponding vertical synchronous signal to a receiving part in case the image data columns in the quantity of n have been stored. Therefore, it becomes possible to increase the process efficiency of the back-end chip and to reduce the power consumption.