Integrated circuit having memory cells and method of manufacture
An integrated circuit having memory cells and a method of manufacture is disclosed. One embodiment provides a switching active volume and a selection transistor coupled in series between a first electrode and a second electrode. The selection transistor is a vertical transistor for at least partiall...
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creator | Gruening-von Schwerin, Ulrike |
description | An integrated circuit having memory cells and a method of manufacture is disclosed. One embodiment provides a switching active volume and a selection transistor coupled in series between a first electrode and a second electrode. The selection transistor is a vertical transistor for at least partially guiding a substantially vertical current flow. The second electrode includes a buried diffused ground plate formed in a substrate. A metal-containing region at least partially contacting the buried diffused ground plate is provided, the metal-containing region at least extending below the selection transistor. |
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One embodiment provides a switching active volume and a selection transistor coupled in series between a first electrode and a second electrode. The selection transistor is a vertical transistor for at least partially guiding a substantially vertical current flow. The second electrode includes a buried diffused ground plate formed in a substrate. A metal-containing region at least partially contacting the buried diffused ground plate is provided, the metal-containing region at least extending below the selection transistor.</description><language>eng</language><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7898006$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64038</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7898006$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Gruening-von Schwerin, Ulrike</creatorcontrib><creatorcontrib>Qimonda AG</creatorcontrib><title>Integrated circuit having memory cells and method of manufacture</title><description>An integrated circuit having memory cells and a method of manufacture is disclosed. One embodiment provides a switching active volume and a selection transistor coupled in series between a first electrode and a second electrode. The selection transistor is a vertical transistor for at least partially guiding a substantially vertical current flow. The second electrode includes a buried diffused ground plate formed in a substrate. A metal-containing region at least partially contacting the buried diffused ground plate is provided, the metal-containing region at least extending below the selection transistor.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZHDwzCtJTS9KLElNUUjOLEouzSxRyEgsy8xLV8hNzc0vqlRITs3JKVZIzEsBCpRk5Kco5Kcp5CbmlaYlJpeUFqXyMLCmJeYUp_JCaW4GBTfXEGcP3dLiAqCpeSXF8UDjQZSBuYWlhYGBmTERSgCp9zJo</recordid><startdate>20110301</startdate><enddate>20110301</enddate><creator>Gruening-von Schwerin, Ulrike</creator><scope>EFH</scope></search><sort><creationdate>20110301</creationdate><title>Integrated circuit having memory cells and method of manufacture</title><author>Gruening-von Schwerin, Ulrike</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_078980063</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Gruening-von Schwerin, Ulrike</creatorcontrib><creatorcontrib>Qimonda AG</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gruening-von Schwerin, Ulrike</au><aucorp>Qimonda AG</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit having memory cells and method of manufacture</title><date>2011-03-01</date><risdate>2011</risdate><abstract>An integrated circuit having memory cells and a method of manufacture is disclosed. One embodiment provides a switching active volume and a selection transistor coupled in series between a first electrode and a second electrode. The selection transistor is a vertical transistor for at least partially guiding a substantially vertical current flow. The second electrode includes a buried diffused ground plate formed in a substrate. A metal-containing region at least partially contacting the buried diffused ground plate is provided, the metal-containing region at least extending below the selection transistor.</abstract><oa>free_for_read</oa></addata></record> |
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recordid | cdi_uspatents_grants_07898006 |
source | USPTO Issued Patents |
title | Integrated circuit having memory cells and method of manufacture |
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