Integrated circuit having memory cells and method of manufacture

An integrated circuit having memory cells and a method of manufacture is disclosed. One embodiment provides a switching active volume and a selection transistor coupled in series between a first electrode and a second electrode. The selection transistor is a vertical transistor for at least partially guiding a substantially vertical current flow. The second electrode includes a buried diffused ground plate formed in a substrate. A metal-containing region at least partially contacting the buried diffused ground plate is provided, the metal-containing region at least extending below the selection transistor.