Phase splitter using digital delay locked loops

Phase splitter using digital delay locked loops

A phase splitter using digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.

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Bibliographische Detailangaben
Hauptverfasser: Lin, Feng, Baker, R. Jacob
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A phase splitter using digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.