Capacitance cell, semiconductor device, and capacitance cell arranging method

A capacitance cell is wired while using adjacent wiring layers Ma and Mb as a pair of electrode layers T and T orthogonally to opposed lateral end faces out of lateral end faces X, X, Y, and Y that section the cell in a plane direction. Contact surfaces of electrode surfaces T and T with the lateral end faces are second connection terminals T and T. For longitudinal pathways, first and second via contact layers V and Vare connected. The first via contact layer V interconnects the wiring layers Ma and Mb. The second via contact layer V is connected to a wiring layer located outside beyond an upper or lower end face Z, Z. The second via contact layer V is connected to a first connection terminal T, T located on the upper or lower end faces Z, Z. The capacitance cells are linked via the first and second connection terminals so that a capacitance element having a free shape is formed. A capacitance cell, a semiconductor device, and a capacitance element arranging method that allow to arrange capacitance elements each using wiring layers sandwiching an interlayer insulating film with less of a leak current as electrode layers according to the shapes of unused areas.