Energy adjusted write pulses in phase-change memory cells

An integrated circuit that includes a plurality of phase-change memory cells, at least one write pulse generator, and at least one temperature sensor. The plurality of phase-change memory cells are each capable of defining at least a first and a second state. The write pulse generator generates a write pulse for the plurality of phase-change memory cells. The temperature sensor is capable of sensing temperature. The write pulse generator adjusts the write pulse for at least some of the phase-change memory cells in accordance with the temperature sensed by the temperature sensor.