One-time programmable cell and memory device having the same

One-time programmable cell and memory device having the same includes a first metal oxide semiconductor (MOS) transistor configured to form a current path between a first node and a second node in response to a read-control signal, a second MOS transistor configured to form a current path between a third node and the second node in response to a write-control signal and an anti-fuse connected between the second node and a ground voltage terminal, wherein a voltage applied to the second node is output as an output signal.