Digital level shifter and methods thereof

A digital level shifter is disclosed that receives an input voltage from a first voltage domain, and provides an output voltage to a second voltage domain. The level shifter includes transistors configured in parallel with input transistors of the level shifter in order to place the output of the level shifter in a determinate state when one of the voltage domains is placed in a low power state. Further, the level shifter includes output transistors configured to equalize a rise time slew rate and fall time slew rate, improving the reliability of the level shifter as the voltage in each voltage domain varies.